Index
FPGA and other programmable logic ICs
FPGA is an integrated circuit that contains many (64 to over 10,000)identical logic cells that can be viewed as standard components.Each logic cell can independently take on any one of alimited set of personalities.The individual cells are interconnected by a matrix of wires and programmableswitches. A user's design is implemented by specifying the simple logic function foreach cell and selectively closing the switches in the interconnect matrix.Complex designs are created bycombining these basic blocks to create the desired circuit.Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device.Depending on the particular device, the program is either 'burned' inpermanently or semi-permanently as part of a board assembly process, or is loaded from an external memory each time the device is powered up. The FPGA has three major configurable elements: configurable logic blocks (CLBs), input/output blocks, and interconnects. The CLBs provide the functional elements for constructing user's logic. The IOBs provide the interface between the package pins and internal signal lines. The programmable interconnect resources provide routing paths to connect the inputs and outputs of the CLBs and IOBs onto the appropriate networks. The Field-Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the intial cost, time delay, and inherent risk of a conventional masked gate array. The FPGAs are customized by loading configuration data into the internal memory cells. Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. There are many different FPGAs with different architectures / processes. There are four main categories of FPGAs currently commerically available: symmetrical array, row-based, hierarchical PLD, and sea-of-gates. In all of these FPGAs the interconnections and how they are programmed vary. Currently there are four technologies in use. They are: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. Depending upon the application, one FPGA technology may have features desirable for that application.
- Static RAM Technology: In the Static RAM FPGA programmable connections are made using pass-transistors, transmission gates, or multiplexers that are controlled by SRAM cells. This technology allows allows fast in-circuit reconfiguration. The major disadvantage is the size of the chip required by the RAM technology and that the chip configuration needs to be loaded to the chip from some external source (usually external non-volatile memory chip). The FPGA can either actively read its configuration data out of external serial or byte-parallel PROM (master mode), or the configuration data can be written into the FPGA (slave and peripheral mode). The FPGA can be programmed an unlimited number of times.
- Anti-Fuse Technology: An anti-fuse resides in a high-impedance state; and can be programmed into low impedance or "fused" state. This technology can be used to make program once devices that are less expensive than the RAM technology.
- EPROM Technology: This method is the same as used in the EPROM memories. The programming is stored without external storage of configuration. EPROM based programmable chip cannot be re-programmed in-circuit and need to be cleared with UV erasing.
- EEPROM Technology: This method is the same as used in the EEPROM memories. The programming is stored without external storage of configuration. EEPROM based programmable chips can be electrically erased but generally cannot be re-programmed in-circuit.
- Creating quasistatic, parameterized FPGA designs - New configuration approaches can lead to easier system designs, benefiting a range of applications. Reducing the overall pin count, interface complexity, and resource usage also enables FPGAs to be a flexible digital-signal-processing alternative to DSP architectures. Rate this link
- EDA tools bridge the system-on-programmable-chip design gap - Once relegated to low-cost, low-capability products, EDA tools for PLD development are becoming more complex to keep up with the increased capacity of the devices. Rate this link
- EDN Programmable-logic directory - The second annual EDN PLD directory highlights the architectures available for your next design. Find out what's new, what's obsolete, and what's evolved in PALs, PLDs, and FPGAs. Rate this link
- Field-programmable devices - field-programmable devices come in a variety of fruity flavors, and more are arriving all the time Rate this link
- FPGA Basics Rate this link
- MRCI FPGA - MRCI maintains one of the most extensive databases on informaion pertaining to FPGAs or Field Programmable Gate Arrays. Rate this link
- FPGAs: a matter of cores - portable logic blocks, or cores, have become an accepted part of ASIC design but using cores in FPGAs presents a new set of challenges Rate this link
- FPGAs and ASICs - This web site is dedicated to the design and use of programmable and quick-turn technologies for space flight applications Rate this link
- FPGAs - Does the performance-power-price product of your software-centric approach no longer compute? Do you need a nimbler platform than a hard-wired ASIC can provide? Programmable logic may be your answer, but carefully calculate the trade-offs to correctly solve your problem. Rate this link
- New FPGA Program Techniques Kick 'But' - Theoretically, FPGAs combine the speed of dedicated, application-optimized hardware with the ability to flexibly change chip resource allocation, so the same system can run many applications, optimized for each one. But FPGAs have historically been so hard to program that it's been very hard and expensive to use these advantages. New tools will help this. Rate this link
- PLD-design methods migrate existing designs to high-capacity devices - moving to newer higher capacity programmable devices can give you higher density and better performance Rate this link
- Programmable logic: Beat the heat on power consumption - Higher performanceand gate countsincrease programmable-logic powerconsumption. Wise device selection and design techniques can significantly improve your chances of coming in under the powerbudget. Rate this link
- Programmable Logic Devices / Programowalne uk.ady logiczne - The site is about programmable logic devices.The site has many links to sites in English and Polish about PLD. Rate this link
- Reconfigurable logic: built-in adaptability - A design based on reconfigurable logic offers both hardware speed and software flexibility. What's it like to design with reconfigurable logic? In this EDN hands-on design project, we find out. Rate this link
- Reconfigurable logic: hardware speed with software flexibility - reconfigurable logic lets you dynamically alter hardware in real time, blurring the boundary between hardware and software Rate this link
- Tutorials for Xilinx and Altera programmable logic with schematic entry and Verilog Rate this link
- EDA tools for FPGAs break down the complexity gridlock - FPGA devices offer execution speed and gate capacity that rivals many ASIC implementations and fosters the growth of EDA tools in that market. Rate this link
FPGA links
Information on Field Programmable Gate Array chips and related techniques.
General information
- GHDL - GHDL is a VHDL simulator, using the GCC technology. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. GHDL compiles VHDL files and creates a binary which simulates (or executes) your design. GHDL does not do synthesis: it cannot translate your design into a netlist. Rate this link
- EDN's Third Annual Programmable-Logic Directory - EDN's PAL, PLD, and FPGA directory highlights the architectures available for your next design. Find out what's new, what's obsolete, and what's evolved in PALs, PLDs, and FPGAs. Rate this link
- fpga4fun - HDL tutorials and designs to promote the use of FPGAs Rate this link
- Emacs Modes for Hardware Languages - This page provides links to existing Emacs modes for languages used in hardware design. Rate this link
- Opencores.org - This is a good site containing free (GPL) tested Verilog/VHDL models. Rate this link
- SOCworks - Site to explore and simulate your System-On-Chip (SOC) ideas and architectures using real vendor IP. Rate this link
- Programmable-logic directory - EDN's fourth annual programmable-logic directory highlights the architectures available for your next design. Find out what's new, what's obsolete, and what's evolved in PALs, PLDs, FPGAs, and ASIC/FPGA hybrids. Rate this link
Resource pages
- Design Entry: In the Digital Design Stage the digital design is created with a schematic digital design editor or a Hardware Description Language (HDL).
- Design Implementation: In the Design Implementation stage, the netlist produced by the design entry program is converted into the bitstream file which configures the FPGA. The first step Maps the design onto the FPGA resources;. The second step Places or assigns logic blocks created in the mapping process in specific locations in the FPGA. The third step Routes the interconnect paths between the logic blocks. The output is a Logic Cell Array File (LCA) for the particular FPGA. This LCA file than then converted into a bitstream file for configuring the FPGA.
- Design Verification: The Design Verification Step tests the design's logic and timing using input stimuli. Various CAE software packages provide verification/simulation tools. In-circuit verification is another way to test the design.
- FPGA Confguration: Configuration is a process in which the circuit design (bitstream file) is downloaded into the FPGA. Through this method the FPGA is configured from within an application program.
- Bringing Parallel Processing to FPGA Designs Rate this link
- CPLDs readily replace precious ?P resources - using CPLDs to offload your CPU lets you create a device that hits an effective performance and cost balance between the conflicting attributes of standard and custom parts Rate this link
- Detailed model shows FPGAs' true costs - an analysis of all the variables affecting IC development shows that FPGAs are extremely cost-effective at surprisingly high production volumes Rate this link
- FPGA makes simple FIFO - FPGA-based, synchronous FIFO that uses the same clock for read and write operations Rate this link
- Introduction to Xilinx Virtex FPGA devices tool - Slide set Rate this link
- Moving beyond programmable logic: if, when, how? - decision to migrate from PLDs and FPGAs to lower cost ASICs seems easy at first glance but may be more complicated than you think, do a little research and analysis before you proceed, and carefully choose which migration path to follow Rate this link
- Navigating Through FPGA Designs - The FPGA design process is not as seamless as one might like. However, powerful synthesis, simulation, and programming tools are here to help. Rate this link
- Navigating Through FPGA Design - FPGA design process is not as seamless as one might like Rate this link
- PLD code reveals pc-board revisions - The PLD code described in this article implements a pc-board-level revision-detection system that detects whether PLD pins are shorted together on a pc board. It is often advantageous to field a single PLD programming file that works for several generations of physical hardware. The PLD needs to understand what the board revision is, so that it can enable or disable functions, pins, or both to external circuitry. Rate this link
- Sequence Control using Programmable Logic - A conceptual level approach, available in modern design tools is used to simplify the task. Rate this link
- The best (or worst?) of both worlds - Programmable-logic devices deliver design, manufacturing, and after-sale-service flexibility that ASICs can't match, but CPLDs and FPGAs also run more slowly, burn more power, and cost more per gate, there is emerging one-chip ASIC/programmable-logic hybrid solutions Rate this link
- Your core, my design, our problem - Integrating third-party cores into a design requires more than just reading a data sheet. Virtual components can greatly enhance design productivity or doom a project to failure, and many factors determine the final outcome. To ensure success, the core provider must become a trusted member of the design team. Rate this link
- A Survey of CORDIC Algorithms for FPGAs - this paper describes the CORDIC algorithm in layman's terms, and discusses implementation issues specific to FPGAs, working copy in pdf format Rate this link
- Distributed Arithmetic - powerful technique for reducing the size of a parallel hardware multiply-accumulate that is well suited to FPGA designs Rate this link
- Multiplication in FPGAs - multiplication is basically a shift add operation, but there are variations how to do it, this document is a brief tutorial on multiplication hardware Rate this link
- The CORDIC Algorithm - class of shift-add algorithms for rotating vectors in a plane Rate this link
- PLD code creates PWM generators - This PLD (programmable-logic-device) code creates arbitrary-resolution, pulse-width-modulated (PWM) generators. PWM generators are useful as low-bandwidth D/A converters in hardware of microprocessor-based systems. When you pass it through a simple RC lowpass filter, a PWM waveform becomes a voltage that's approximately equal to the PWM duty cycle times the supply voltage. This code is written for Altera's devices, but you can quite easily translate the design structure and flow into VHDL or Verilog. Rate this link
- Preprocessor for rotary encoder uses PAL - Rotary encoders usually provide quadrature pulses that indicate both the amount of rotation and the direction. This application idea helps keeping accurate track of rotary encoder position. Rate this link
- XAPP052: Efficient Shift Registers, LFSR Counters and Long Pseudo-Random Sequence Generators - FPGA application note from Xilinx in pdf format Rate this link
- VCO uses programmable logic - A VCO (voltage-controlled oscillator) is an analog circuit, so you cannot find it in the libraries for the design of digital programmable chips. When you need such a circuit for synchronization or clock multiplication, you need to find a circuit that works with the standard digital functions, such as AND and NAND. Several possibilities exist for building variable-frequency oscillators. This design modifies a two-NOR-gate RC oscillator to function as a VCO. Rate this link
- A Dynamic Hardware Video Processing Platform - paper examines use of an FPGA as the processing element in a video processing system, pdf format Rate this link
- DSP design tools target FPGAs - fast DSP algorithms demand a hardware implementation Rate this link
- DSP woth FPGAs - nice tutorial document collection Rate this link
- Fastand flexible: FIR filters in reconfigurable logic - reconfigurable logic lets you implement DSP functions in hardware, providing a mix of speed and design flexibility that isn't available in DSPs or mask-programmed ASICs, filter design tools make design tasks easy Rate this link
- FIR filter fits in an FPGA: A bit serial Approach - presentation of design techniques to realize a 27 tap 12 bit FIR filter in a single FPGA, pdf format Rate this link
- Modulation and Demodulation Techniques for FPGAs - presentation slides from a presentation of digital demodulation for FPGAs, includes implementation of an IS-95 North American Cellular Modem in a Xilinx 4013 as an example Rate this link
- Soft Radios and Modems on FPGAs Rate this link
- 10 tips for successful scan design: part one - As gate counts increase at an enormous rate, the scan-design methodology is becoming necessary to produce high-quality chips Rate this link
- 10 tips for successful scan design: part two - 10 design principles to follow for successful implementation of scan-test techniques Rate this link
- In-system programmable logic simplifies prototyping to production - changing a programmable device so that it can be programmed in a system after the device is mounted on a pc board benefits prototype development, manufacturing, and field support Rate this link
- Program ICs in your system via IEEE 1149.1 and enjoy the benefits throughout the system's life Rate this link
- Simple boundary-scan techniques tackle sophisticated systems - If you think that boundary-scan techniques are old news, think again. Today's new packaging technology is forcing test engineers to revisit old technologies. Meanwhile, flash memories and deeply embedded systems are continuously driving boundary-scan developments. Rate this link
- You need little more than a PC to test and program IEEE-1149.1-compliant ICs - if the products youre testing support boundary scan, expensive testers and extra equipment may even be unnecessary in production, you just need a simple adapter between your card and your PC Rate this link
- Asynchronous circuit divides frequency by 1.5 Rate this link
- Counter provides divide-by-4.5 function - some VHDL code, a 9-bit shift register, and some OR gates produce a divide-by-4.5 circuit, you can can adapt the concept for other noninteger dividers Rate this link
- Delay line implements clock doubler - using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock Rate this link
- VHDL code implements 50%-duty-cycle divider - realizing a 50%-duty-cycle, divided-down clock is not always a trivial task, particularly when the divisor rate is an odd number but this example code will help youn in this task Rate this link
- Careful PCB Layout Enhances Onboard Programming - PCB design techniques that can help you effectively employ onboard programming to speed the production and test of products containing complex programmable-logic devices Rate this link
- Circuit protects FPGAs from killer spikes Rate this link
- High-end digital systems give a thumbs down to rules of thumb - lower voltages, higher current transients, and higher clock rates render rules of thumb uselsss for designing power-distribution-system decoupling networks Rate this link
- Decoder safely drives data-bus buffer - a common way of implementing an I/O decoder for the ISA (or similar) bus Rate this link
- Distributed-DMA techniques allow easy migration from the ISA bus to the PCI bus - a technique using distributed DMA offers upward compatibility for ISA-legacy devices in PCI-bus systems and provides a vast improvement in performance Rate this link
- FPGA memory controller links embedded ?P to cache-enhanced DRAM Rate this link
- FPGAS: Implementing the PCI Interface Rate this link
- FPGA transfers data on every clock cycle - static-RAM (SRAM) interface Rate this link
- Shared-memory interface eliminates arbitration Rate this link
- Use a CPLD to implement an SDRAM controller - SDRAM-controller designs need not be especially difficult Rate this link
- Create your own VGA system with Altera FPGA - Altera FPGA VGA synchronization for everyone Rate this link
- Fast integer multipliers fit in FPGAs - You can fit a fast and compact digital multiplier into a field-programmable gate array (FPGA). The technique involves using small look-up tables to find partial products and then adding the partial products. The key factor for making the design compact, fast, and easy to implement is to make the look-up tables for the partial products as small as possible. This multiplier can quickly multiply a number by a constant. Rate this link
- FPGA circuit emulates 74X74 flip-flop Rate this link
- FPGA's tri-state buffers build 32x32 crossbar - A network of tri-state buffers in the XC4025 FPGA (field-programmable gate array) makes a 32?32-pair crossbar switch possible. The design uses input and output pipelining, and the crossbar switch's throughput is 100 Mbps for each 2-bit channel. Rate this link
- Integers out of sorts? Program an FPGA to put them in order - designing integer-sort algorithms into FPGAs isn't as difficult as you might think Rate this link
- Look-ahead approach tames large FPGA counters - the T flip-flops and look-ahead technique allow you to program large, fast counters in FPGAs Rate this link
- Modulator's design cuts FPGA's gate count - pulse-width modulator (PWM) macro requires only half as much logic as a conventional 2-counter design Rate this link
- Priority encoders slip into FPGAs - The standard 8-to-3 priority encoder's design, in maximal canonical form (such as the 74148), suffers from drawbacks when you try to use the design as a macro in a large digital project. The simplified approach shows a 2-to-1 priority encoder, which generates the proper output as well as a signal-present output (SP). SP indicates the presence of any signal at the inputs, simplifying testing. Combine two basic building blocks into a 4-to-2 priority encoder. Also 8-to-3 encoder is presented as an example. Extending this design to 16 or more inputs is not advisable. Rate this link
- Simple monovibrator uses three PLD pins - if you can afford just three spare PLD pins, this circuit is an alternative to using yet another 555 Rate this link
- Verilog program models metastable flip-flop - HDL program allows you to simulate the behavior of a set-reset (SR) flip-flop that has both its set and reset inputs high simultaneously Rate this link
- VGA Generator that displays an image in the XS Board RAM on a VGA monitor - example of using Virtex series FPGA to generate VGA signals Rate this link
Design tips
Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. There are many different FPGAs with different architectures / processes. The standard digital design flow for FPGA programming:
General
Arimethics using FPGAs
Counters
Oscillator
Signal processing using FPGAs
Digital signal processing has traditionally been done using enhanced microprocessors but recent increases in Field Programmable Gate Array performance and size offer a new hardware acceleration opportunity.
System and design testing and programming
Clock generation and division
Circuit design around FPGA chip
Computer interfacing
Telecommunication applications
Other tips
- Design and Reuse Web site - D&R provides a global collaboration network for sharing design resources in the electronics SoC industry Rate this link
- Getting a handle on HDLs - Programmable-logic chips and designs are growing more complex. As a result, you?ll sooner or later need to add HDL expertise to your skills if you want to keep hitting those project deadlines. For this Hands-On Project, I learn VHDL, complete a mixed logic and embedded-memory design in an FPGA, and share observations along the way. Rate this link
- Interfacing HDLs with conventional programming languages - programming languages that interface with HDL models facilitate hardware/software codesign Rate this link
- 10 tips for generating reusable VHDL - Your ability to reuse blocks expressed in an HDL is critical to designing systems on chips. Here are some tips you can use to generate VHDL-based blocks that you and others can reuse in subsequent chip designs. Rate this link
- HDL basic training: top-down chip design using Verilog and VHDL Rate this link
- Using VHDL-AMS to model complex heterogeneous systems, part 1 - HDLs bridge the gap between math-based tools and physics-based tools to help you meet model-development requirements. Rate this link
- Using VHDL-AMS to model complex heterogeneous systems, part 2 - You can implement DSP-controller algorithms using the mixed-signal features of the VHDL-AMS modeling language. Rate this link
- VHDL and Verilog fundamentals--expressions, operands, and operators - data objects in VHDL and Verilog form expression operands, knowing the operand differences between the two HDLs helps you write more efficient chip-design code Rate this link
- VHDL and Verilog fundamentals--design entities, data types, and data objects Rate this link
- VHDL emerges as a commercial design tool - despite the initial challenges imposed by VHDL, the language, born of the military, has made the commercial sector sit up and take notice Rate this link
- VHDL Synthesis Tutorial Rate this link
- Simulating mixed-mode designs with Verilog-only models - PLL circuits offer developers of mixed-signal designs a unique challenge. Commonly used as frequency synthesizers, clock multipliers, or clock-recovery devices, PLLs are crucial to many microcontrollers and microprocessors. As more functions enter the digital domain, verification becomes more difficult and requires more sophisticated models. A Verilog-only model can solve most of these problems. Rate this link
- The C Programmers Guide to Verilog - Now that hardware is designed in high-level languages, the fields of hardware and software development are beginning to merge. Here's an introduction to hardware design in Verilog for the uninitiated. Rate this link
- Verilog FAQ Rate this link
- HDL basic training: top-down chip design using Verilog and VHDL Rate this link
- VHDL and Verilog fundamentals--expressions, operands, and operators - data objects in VHDL and Verilog form expression operands, knowing the operand differences between the two HDLs helps you write more efficient chip-design code Rate this link
- VHDL and Verilog fundamentals--design entities, data types, and data objects Rate this link
- CynApps Cynlib - C++ based hardware description language Rate this link
- LavaLogic - Java-based synthesis tool Rate this link
- SpecC Rate this link
- Superlog - superset of Verilog, borrows features from VHDL and C++ Rate this link
- SystemC - modeling platform that enables, promotes and accelarates system-level co-design and IP exchange Rate this link
- EDA.ORG - dedicated to the support, open exchange and dissemination of in-development standards from EDA Industry Working Groups Rate this link
- European Electronics Chips and Systems Design Initiative (ECSI) Rate this link
- Gigascale Silicon Research Center Semantics Project Rate this link
- The Free Model Foundry - The Free Model Foundry (FMF) promotes the development and free distribution of open source models of electronic components in system design. Rate this link
- VHDL International - organization dedicated for promoting VHDL as a standard description language for electronics systems Rate this link
VHDL and other hardware description languages
Hardware description languages are essential tools for handlingthe increasing complexity of the hardware designs.Information on VHDL hardware description language that is usedfor designing logic circuits implemented with FPGA or ASIC technologies.VHDL is a way of describing the desired operation of a logic device. Although it is a standard, vendors all choose different parts to implement and add their own quirks.In VHDL synthesis, we describe a program that would have the same behavior as the circuit we wish to create. This program is used by the synthesis tools to create the configuration file that will configure the specific FPGA or PLD into a correct circuit. The syntax is very similar to Ada.
General
VHDL
Verilog
Other languages
Organizations
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